Fine Pitch Flip-Chip Bump Technology

Introduction

Heterogeneous structure, 3D stack package, and other techniques are suggested as solutions for SoC (System on Chip) development that will accelerate even further in the future. SHINKO has developed fine pitch flip-chip bump technology to provide these products by fusing the plating technology (for semiconductor packages) with thin film technology and other technologies.

Fine Pitch Flip-Chip Terminals

Taking advantage of SHINKO's core plating technology, we developed next-generation bump structure with a pitch of 30μm and a pat diameter of 20μm by using Ni/Pd/Au plating processes as organic-substrate final surface treatment with high joint reliability.

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We are now developing next-generation technology for connecting terminals having narrower-pitch high mounting reliability structure and soldering structure.

Electroless Pd/Au Plating Technology

As electroless Pd/Au plating is made directly on a Cu bump, superior plating precipitability and high implementation reliability are provided. finer-pitch can be achieved because it lacks the Ni layers used in the conventional structure.

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Electrolytic Sn Plating Technology

As Ni/Sn plating is applied directly to a Cu bump, soldering is only possible on the top surface. Since IC chip size has become larger in recent years, problems such as warp and waviness have become apparent. However, we offer semiconductor packaging solutions for these issues.

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